This invention relates to a design technology for an integrated circuit and, more particularly, to a method for estimating parasitic capacitance coupled to a conductive pattern forming a part of an integrated circuit.
Various circuit components are fabricated on a semiconductor substrate, and conductive strips are selectively connected to the circuit components for forming an integrated circuit on the semiconductor substrate. The conductive strips are multi-layered, and inter-level insulating layers are inserted between the conductive strips on different levels.
The conductive strips and the gap therebetween have been getting narrower and narrower, and the inter-level insulating layers have become thinner. For this reason, it is necessary for the designer to exactly evaluate the parasitic capacitance between the conductive strips on an inter-level insulating layer and the parasitic capacitance between the conductive strip on the inter-level insulating layer and the conductive strip over or under the inter-level insulating layer. The parasitic capacitance retards the signal propagation on the conductive strip. The manufacturer calculates the parasitic capacitance coupled to each of the conductive strips, and simulates the circuit behavior of the integrated circuit.
A typical example of the estimation starts with dividing a signal line into parts, and each of the parts is compared with samples in a database. The parasitic capacitance of each sample is known, and the parasitic capacitance of each part is determined by selecting one of the samples. Finally, the parasitic capacitances of the parts are added together, and the parasitic capacitance of the single line is finally determined.
FIG. 1 illustrates the prior art method for estimating the parasitic capacitances of interconnection. The layout of an integrated circuit is assumed to be designed. Circuit components and interconnections form the integrated circuit. Most of the interconnections serve as signal lines. Firstly, a signal line is extracted from the integrated circuit as by step S200. The signal line is divided into parts such as those on a grating as by step S201. All the parts have a unit length.
The prior art method proceeds to step S203, and one of the parts is extracted. The environment around the extracted part is analyzed as by step S204. In the analysis, it is considered what kind of circuit components is closed to the extracted part. The dimensions of an adjacent signal line, the distance therefrom and the material of the layers therearound are further considered. A capacity parameter table and a mathematical expression have been already prepared for calculating a capacitance as by step S205 and S206. When the environment is determined, capacity parameters approximated to the extracted part are selected from the capacity parameter table, and a parasitic capacitance is calculated by substituting the selected parameters into the mathematical expression. Then, a parasitic capacitance is determined as by step S207.
Then, the control checks the signal line to see whether or not the parasitic capacitances are calculated for all the parts as by step S208. If the answer at step S208 is given negative, the control returns to step S203, and reiterates the loop consisting of steps S203 to S208. When the capacitances are determined for all the parts, the answer at step S208 is given affirmative, and the control proceeds to step S209.
The control calculates the total of the capacitances at step S209, and checks the conductive pattern to see whether or not the parasitic capacitances are determined for all the signal lines as by step S210. When there is another part to be estimated, the answer at step S210 is given negative, and the control returns to step S200. While the answer at step S210 is given negative, the control repeats the loop consisting of steps S200 to S210. When the parasitic capacitance is calculated for all the signal lines, the answer at step S210 is given affirmative, and the control reaches xe2x80x9cendxe2x80x9d. Japanese Patent Publication of Unexamined Application No. 6-120343 discloses a method like the prior art method described hereinbefore.
The prior art method takes the environment around each part of the signal line into account, and the analyst can accurately estimate the parasitic capacitance by using the prior art method. However, a problem is encountered in the prior art method in that the estimation consumes a long time. This is because of the fact that the control repeats the loop consisting of steps S203 to S208 for a signal line and the loop consisting of steps S200 to S210 for the integrated circuit.
It is therefore an important object of the present invention to provide a method for estimating parasitic capacitances of wiring within a short time.
The present inventor contemplated the problem inherent in the prior art method. The present inventor noticed that the parasitic capacitance was proportional to the length of the signal line in so far as the signal line exceeded a critical length. The present inventor concluded that signal lines longer than the critical length did not require the repetition of the calculation.
In accordance with one aspect of the present invention, there is provided a method for estimating a parasitic capacitance coupled to a signal line forming a part of an integrated circuit incorporated in a semiconductor device, and the method comprises the steps of a) preparing a first piece of data information indicative of a minimum length for calculating a parasitic capacitance as a function of the length of a signal line, a second piece of data information indicative of a capacitance considered to be coupled to a unit length of signal lines and third pieces of data information used for estimating the parasitic capacitance coupled to a signal line through a known method, b) determining the length of a given signal line, c) comparing the length of the given signal line with the minimum length so as to determine whether or not the function is available for determining the parasitic capacitance coupled to the given signal line, d) determining the parasitic capacitance coupled to the given signal line by using the function once when the given signal line is equal to or greater than the minimum length and e) determining the parasitic capacitance coupled to the given signal line by using the known method without execution of the step d) when the given signal line is less than the minimum length.